In an Si (silicon) MOSFET (Metal Oxide Semiconductor Field Effect Transistor) representing a widely used power semiconductor device, a main factor determining a breakdown voltage is an upper limit of electric field intensity which a drift layer forming a breakdown voltage holding region can withstand. A drift layer made of Si may break down at a portion where electric field not lower than approximately 0.3 MV/cm is applied. Therefore, it is necessary to suppress electric field intensity to be less than a prescribed value in the entire drift layer of a MOSFET. The simplest method is to lower an impurity concentration in a drift layer and to increase a thickness of the layer. This method, however, is disadvantageous in high ON resistance of a MOSFET. Namely, there is trade-off relation between ON resistance and a breakdown voltage.
Japanese Patent Laying-Open No. 9-191109 (PTD 1) describes trade-off relation between ON resistance and a breakdown voltage in connection with a typical Si MOSFET, taking into consideration a theoretical limit obtained from a physical property value of Si. Then, in order to overcome this trade-off, it has disclosed addition of a lower p-type embedded layer and an upper p-type embedded layer in an n base layer on an n-type substrate on a drain electrode. The lower p-type embedded layer and the upper embedded layer divide the n base layer into a lower portion, a middle portion, and an upper portion equal to one another in thickness. According to this document, an equally divided voltage is applied to the three portions and maximum electric field of each portion is kept at limit electric field intensity or lower.